1. Field of the Invention
The present invention relates to a method and device for combining at least two data signals having a first data rate into a single data stream having a second data rate being higher than the first data rate for transmission on a shared medium and vice versa. Particularly, the present invention relates to a method and device for combining 84 T-1 (DS-1) channels of 1.544 Mb/s (megabits per second) each into one STM-1 frame corresponding to 155 Mb/s and 63 E-1 channels of 2.048 Mb/s each or 21 T-2 (DS-2) channels of 6.312 Mb/s each into one STM-1 frame, respectively. However, the concept of the present invention is also applicable for different protocols or other hierarchical levels of the SDH or SONET standard as apparent from the following description.
2. Description of the Related Art
The American National Standards Institute has established a standard for high-speed, multiplexed digital data transmission. This is the “synchronous optical network” standard, henceforth referred to as SONET. The SONET standard specifies optical interfaces, data rates, operation procedures and frame structures for multiplexed digital transmission via fiber optic networks.
The International Telecommunications Union (ITU) has adopted the Interface principles of SONET and recommended a new global transmission standard for high-speed digital data transmission. This standard is the “synchronous digital hierarchy” (SDH).
For an account of the SDH standard, reference should be made to the report 30 entitled “REPORT OF Q.22/15 MEETING” from “STUDY GROUP 15” of the ITU International Telecommunication Standardization Sector, bearing the document number “Temporary Document 62(3/15)” and the date “Geneva, 16-27 May 1994.”
The SDH standard is designed to enable manufacturers to develop telecommunications equipment which:    a) will be interchangeable in all telecommunication networks built around the world to its standard; and which    b) is backwards compatible, i.e. can be used with data which is in the older telecommunications formats used in North America, Europe and Japan.
This is achieved by a complex hierarchy of so-called “Containers” (C) and “Virtual Containers” (VC), see FIG. 1. The container, e.g. C-4, C-3, C-12, etc., are information structures designed to accommodate data traffic with specific transmission rates. The C-4 carries traffic with a base rate of up to 139264 kbit/s, the C-3 container carries either up to 44736 or 34368 kbit/s, etc. The containers are turned into virtual containers by adding Path Overhead information (POH) to it. By procedures defined as multiplexing, mapping, or aligning, data structures are generated which are constitutive to the SDH. These data structures are named “Administrative Unit Groups” (AUG) and “Synchronous Transport Module” (STM). The label of an STM is defined by the number of AUGs it carries: a STM-4 contains for example four AUGs. An AUG contains either one “Administration Unit” (AU) of type AU-4 or three of type AU-3. Referring to the simplest cases, in turn one AU-4 contains one C-4 signal and one AU-3 carries one C-3 signal.
The SDH/SONET data frames, i.e., the STM-N signals, are 125 microseconds long. The amount of data transmitted in each frame depends on the hierarchy level N of the signal. The higher hierarchical levels are transmitted at higher data rates than the basic STM-1 level of approximately 155 Mbit/s. The exact transmission rate is defined as 155.52 Mbit/s. However, here and in the following transmission rates are often denoted by their approximate values. This is, in particular, due to the fact that the exact data transmission rates are distorted by overhead data traffic and idle cell stuffing. The integer N indicates how many times faster the data is transmitted than in the STM-1 level. For example STM-4 denotes a data transmission rate of 622 Mbit/s, whereby each data frame contains four times as many bytes as does a frame of STM-1. The highest defined level is STM-64, which has a data rate of 9.95 Gb/s. Hence, each part of the STM-N signal is broadcast in the same time as the corresponding part of an STM-1 signal, but contains N times as many bytes.
The STM-1 signal, as shown in FIG. 2, contains an information rectangle of 9 rows with 270 bytes/row corresponding to a SONET/SDH data rate of 155.52 Mbit/s. The first 9 bytes/row represent the “Section Overhead” henceforth SOH. The remaining 261 bytes/row are reserved for the VCs, which in FIG. 1 is a VC-4. The first column of a VC-4 container consists of the “Path Overhead” (POH). The rest is occupied by the payload (a C-4 signal). Several VCs can be concatenated to provide a single transmission channel with a corresponding bandwidth. For example, four VC-4 in a STM-4 signal can be concatenated to form a single data channel with approximately 600 Mbit/s capacity: in this case the four VCs are referred to in the standard terminology as VC-4-4c and the signal as STM-4c.
This flexibility of the SDH standard is partly due to the pointer concept: In SDH, the frames are synchronized, but the VCs within them are not locked to the frames. So the individual containers of the SDH signals do not have to be frame aligned or synchronized amongst each other. A “pointer” is provided in the Section Overhead which indicates the position of the above introduced POH, i.e., the start of a virtual container in the SDH frame. The POH can thus be flexibly positioned at any position in the frame. The multiplexing of information into higher order SDH frames becomes simpler than in the old data standards, and an expensive synchronization buffer is not required in SDH. Similarly, lower order signals can be extracted out of and inserted into the higher order SDH signals without the need to demultiplex the entire signal hierarchy. The pointers are stored in the fourth row of the Section Overhead.
The Section Overhead is further subdivided into: (i) The “Regenerator Section Overhead” or RSOH. This portion contains bytes of information which are used by repeater stations along the route traversed by the SONET/SDH Signal. The Regenerator Section Overhead occupies rows 1-3 of the Section Overhead. (ii) The “Multiplexer Section Overhead” or MSOH. This contains bytes of information used by the multiplexers along the SONET/SDH signal's route. The Multiplexer Section Overhead occupies rows 5-9 of the Section Overhead. These sections of the overhead are assembled and dissembled at different stages during the transmission process. FIG. 2 also shows an exploded view of the MSOH.
In the parallel SONET system, a base signal of 51.84 Mbit/s is used. It is called the Synchronous Transport Signal level 1, henceforth STS-1. This has an information rectangle of 9 rows with 90 bytes/row. The first three bytes/row are the section overhead and the remaining 87 bytes/row are the “synchronous payload envelope”, henceforth SPE. Three of these SPEs fit exactly into one Virtual Container-4. Thus signals in the STS-1 signal format can be mapped into an STM-1 frame. Furthermore, frame aligned STS-1 or STM-1 signals can be multiplexed into higher order STM-N frames.
In general, any lower data rate signal which is combined with other such signals into new data frames of higher rate is referred to as a “tributary” signal. For example in the previous paragraph, the three STS-1 signals which are combined into one STM-1 signal are tributary signals. It may be noted that the scope of the term tributary in this description exceeds the standard definition, as it is also used to describe the inter-level signal mapping in SDH.
The present invention relates to a data processing module for mapping data, i.e. tributaries, into and out of the SDH/SONET formats. The data processing achieved with the present invention concerns in particular the compilation of data which is at relatively low data rates into standard data frames of relatively high data rate, and vice-versa.
U.S. Pat. No. 5,452,307 describes a general data multiplexing system comprising a plurality of data multiplexing buses through which a plurality of low-speed digital signals are collected into, and distributed from, a multiplexer/demultiplexer. In a data multiplexing mode, the low-speed digital signals entered from a plurality of low-speed transmission lines have their signal format converted by respectively corresponding low-speed interface circuits, and the resulting signals are multiplexed in time slots designated within a multiplexed signal of primary level on the up bus line of the corresponding data multiplexing bus, under the controls of respectively corresponding bus control circuits. The high-speed multiplexer collects the primary multiplexed signals on the up bus lines of the plurality of data multiplexing buses, and further multiplexes the collected signals up to a predetermined signal level. Thereafter, it sends the resulting secondary multiplexed signal to a high-speed interface module having a high-speed transmission line interface. The high-speed interface module converts the received secondary multiplexed signal so as to match the interface of a high-speed transmission line, and sends the resulting signal to the high-speed transmission line. In a data demultiplexing mode, the signal of the high-speed transmission line is processed by the high-speed interface module and the high-speed demultiplexer, and the resulting signals are distributed through the down bus lines of the data multiplexing buses so as to send the low-speed digital signals to the low-speed transmission lines.
In M. Stadler et. al., “An Embedded Stack Microprocessor for SDH Telecommunication Applications”, in Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (CICC'98), Santa Clara, Calif., USA, May 11-14, 1998, a microprocessor is disclosed which is integrated on the same die as the complete data path of a SDH Add-Drop Multiplexer (ADM). It handles over 1 Million interrupts per second from 29 asynchronous sources. The multiple asynchronous data sources are each connected either to multiple VC-3 mapping units (also called “mapper”) or to multiple VC-12 mapping units for overhead processing. On one hand, each VC-3 mapping unit is coupled to a TU-3 framing unit (also called “framer”) that also takes care of the pointer processing in order to facilitate the frequency adaption between the asynchronous data sources and the clock rate of the higher hierarchy levels. On the other hand, each VC-12 mapping unit is linked to a TU-12 framing unit that also takes care of the pointer processing in order to facilitate the frequency adaption between the asynchronous data sources and the clock rate of the higher hierarchy levels. Subsequently, all TU-3 and TU-12 framing units are combined into one data stream by a VC-4 mapping unit that itself is linked to a AU-4 framing unit for pointer processing and, thereafter, the data steam reaches a STM-1 framing unit, between each framing or mapping unit a different frequency area being realized.
With the increasing mix of voice and data on SDH/SONET networks there is a huge need for mapping low-speed plesiochronous digital hierarchy (PDH), i.e., a transmission system for voice communication using plesiochronous synchronization, channels into high-speed synchronous digital hierarchy (SDH) frames. This is presently done in a system such as the described above in M. Stadler et. al.
European patent application EP 0 874 487 A2 discloses a method, in which at least two data signals having a first data rate are multiplexed into a single data stream having a second data rate being higher than the first data rate for transmission on a shared medium or vice versa. Supercarrier control signals are generated. A supercarrier transmitter maps the supercarrier data signals and the supercarrier control signals into an output supercarrier signal of a high bit rate, and transmits same over high rate span. However, European patent application EP 0 874 487 A2 does not disclose a detailed solution for offering complete SDH/SONET processing for M low-speed channels in a single line of processing units operating at M times the speed of the low channels without the need of any further buffer in the data path behind the ports. Therefore it is difficult to implement the whole device using one single integrated circuit. Thus, it is a problem to construct the device with all its memories on one and the same chip.
Starting from this, it is an object of the present invention to provide a method and device to more efficiently perform the function of combining at least two data signals having a first data rate into a single data stream having a second data rate being higher than the first data rate for transmission on a shared medium and vice versa.